An integrated circuit contains millions of transistors, capacitors and resistors on a single chip. Integration of various elements is done by forming conductive lines, such as metals, heavily doped polycrystalline silicon. As wafers have become larger and circuit scales become smaller, the interconnect conductive lines and associated dielectric materials that facilitate wiring between the transistors and other devices play more and more important role on IC performance improvement. Studies and researches are heavily conducted to search not only new conductive and dielectric materials but also new process integration schemes for a better interconnection. New interconnection materials are explored, such as integrating copper metallurgy in place of traditional aluminum to reduce the resistance component of the RC time delay, integrating a new insulating material with a lower dielectric constant (k) than the incumbent silicon dioxide to reduce the capacitance component as well as cross-talk between conductive lines to minimize time delay and power dissipation. When designing a new interconnection process scheme, there are numbers of concerns to be taken into consideration, such as the aspect ratio (AR) of the vias and trenches, the quality of metal filling in, sidewall protection of side of metal, minimizing process-induced-damage on insulation dielectric layers, good process control as well as low manufacture cost and high production throughput. Although existing approaches have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.
In semiconductor technology, an integrated circuit pattern can be formed on a substrate using various processes including a photolithography process, ion implantation, deposition and etch. Damascene processes are utilized to form multilayer copper interconnections including vertical interconnection vias and horizontal interconnection metal lines. During a damascene process, trenches are formed in a dielectric material layer, copper or tungsten is filled in the trenches, then a chemical mechanical polishing (CMP) process is applied to remove excessive metal on the dielectric material layer and planarize the top surface.
As the integrated circuit (IC) fabrication moves to advanced technology nodes, the IC feature size scales down to smaller dimensions. For example, the trench dimensions get smaller and smaller. Accordingly, the gap-filling ability of those metallic material is limited and the gap-filling quality and reliability are challenged. Further, the corresponding conductivity of the gap-filling metal is needed to be higher for desired performance of the interconnect structure. Thus, the interconnect material is a bottle neck for further improving the interconnect structure with required performance and reliability. Accordingly, a structure of interconnect structure and a method making the same are needed to address the above issues.